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9X14 mm SMD, 3.3V, LVPECL
Frequency Range: Frequency Stability:
CCPD-920 Model
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50MHz to 150MHz 20, 25, 50ppm (0C to 70C) 25, 50ppm (-40C to 85C) Temperature Range: 0C to 70C (Option X) -40C to 85C Storage: -55C to 120C Input Voltage: 3.3V 0.3V Input Current: 88mA Max Output: Differential LVPECL Symmetry: 45/55% Max @ 50% Vdd Rise/Fall Time: 1ns Max @ 20% to 80% Vdd Linearity: 10% Max Logic: Terminated to Vdd-2V into 50 ohms Logic "0" "0" = Vcc-1.85V Min, Vcc-1.62V Max Logic "1" "1" = Vcc-1.02V Min, Vcc-0.81V Max Disable Time 200ns Max Start-up Time 1ms Typ., 2ms Max Phase Jitter: 12KHz to 80MHz 0.5psec Typ., 1psec RMS Max Phase Noise: 10Hz -65dBc/Hz Typical 100Hz -98dBc/Hz Typical 1KHz -125dBc/Hz Typical 10KHz -140dBc/Hz Typical 100KHz - 100MHz -145dBc/Hz Typical
Differential LVPECL Clock Oscillator
Designed to meet today's requirements for 3.3V Differential LVPECL applications. The CCPD920 is produced using our cost saving FR5 PCB and UM-1 overtone crystal technology. This design offers considerable cost savings over other HFF XO's products. Also available in 14 pin dip fully hermetic package.
Aging:
<3ppm 1st/yr, <1ppm every year thereafter SUGGESTED PAD LAYOUT
0.560 (14.2)
Bottom View
0.560 (14.2) 0.210 (5.3)
0.050 (1.27)
0.360 (9.14)
CRYSTEK P/N Frequency Date Code
1 6
0.100 (2.54)
2 5
3 4
0.040 (1.01) 0.070 (1.77) 0.090 (2.28) 0.280 (7.11)
0.200 (5.08)
RECOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE
260C 217C 200C 150C
Ramp-Up 3C/Sec Max. Critical Temperature Zone Ramp-Down 6C/Sec.
Crystek Part Number Guide CCPD-920 X - 25 - 100.000
#1 #2 #3 #4 #5
Stability Indicator:
#1 Crystek 9x14 SMD PECL OSC #2 Model 920 #3 Temp. Range: Blank = 0/70C, X=-40/85C #4 Stability: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places 20 = 0/70C(20ppm) 25 = 0/70C (25ppm) 50 = 0/70C (50ppm) 25 = -40/85C (25ppm) 50 = -40/85C (50ppm)
Preheat 180 Secs. Max. 8 Minutes Max.
90 Secs. Max.
260C for 10 Secs. Max. NOTE: Reflow Profile with 240C peak also acceptable.
Table 1
Example: CCPD-920X-25-100.000 = 3.3V, 45/55, -40/85C, 25ppm, 100.000 MHz
Enable/Disable Function Pin 2 Output Pin Open Active "0" level Vcc-1.620V Max Active "1" level Vcc-1.025V Min Disabled Disabled State: Pin 4 will assume a fixed level of logic "0" Pin 5 will assume a fixed level of logic "1"
Pad 1 2 3 4 5 6
Connection N/C E/D GND OUT COUT Vdd Specifications subject to change without notice.
TD-051101 Rev. B

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